One of the components of an integrated circuit chip is an array of bond pads for electrically connecting the chip to other components of the system in which it is utilized. The bond pad array typically includes multiple bond pads located around the periphery of the integrated circuit chip. Each bond pad is a conductive area used for bonding a connecting wire, the other end of which is connected to a pin of the integrated circuit package. Interface circuitry, such as electrostatic discharge (ESD) protection circuitry and level shifting circuitry, may be associated with the bond pad.
In a common approach, bond pads and associated circuitry are positioned adjacent to each other on a chip. A top schematic view of a prior art bond pad structure is shown in FIG. 1. A bond pad 10 is located at the periphery of an integrated circuit chip 12. Bond pad 10 may be a conductive metal having a sufficient area for bonding of a connecting wire. An ESD protection circuit 20 is located adjacent to and electrically connected to bond pad 10. ESD protection circuit 20 may include PMOS ESD/buffer transistors 22 located under a power supply bus 24 and NMOS ESD/buffer transistors 26 located under a power return bus 28. An isolation/control logic block 30, located between PMOS transistors 22 and NMOS transistors 26, includes control logic and provides isolation between PMOS transistors 22 and NMOS transistors 26. As is apparent from FIG. 1, the prior art bond pad 10 and ESD protection circuit 20 occupy significant chip area. The required area is multiplied by the number of I/O pins on the chip.
Integrated circuits have undergone dramatic increases in function and performance, and dramatic decreases in feature sizes. These trends have impacted the requirements for bond pad structures. As device features have become smaller, the ESD pulse that an integrated circuit is required to withstand has remained the same. Although the density of other circuits has increased, the chip area required to dissipate the ESD pulse has remained nearly constant. In addition, the number of bond pads on a chip has increased with increasing circuit complexity. These trends have resulted in bond pads and ESD protection circuitry occupying a significant proportion of the total chip area on state of the art integrated circuits. It is not uncommon for bond pads and related circuitry to occupy 10–15% of the die area in state of the art integrated circuits.
Various designs for ESD protection circuits and bond pads have been disclosed in the prior art. See, for example, U.S. Pat. No. 5,514,892, issued May 7, 1996 to Countryman et al.; U.S. Pat. No. 5,517,048, issued May 14, 1996 to Kosaka; U.S. Pat. No. 5,751,065, issued May 12, 1998 to Chittipeddi et al.; U.S. Pat. No. 5,901,022, issued May 4, 1999 to Ker; U.S. Pat. No. 6,157,065, issued Dec. 5, 2000 to Huang et al.; U.S. Pat. No. 6,207,547, issued Mar. 27, 2001 to Chittipeddi et al; U.S. Pat. No. 6,384,486, issued May 7, 2002 to Zuniga et al; and W. R. Anderson et al. “ESD Protection Under Wire Bonding Pads”, EOS/ESD Symposium 99–89, pp. 2A.4.1–2A.4.7.
It has been proposed in the prior art to fabricate ESD protection circuitry underneath bond pads. One of the difficulties in this approach is that the bond pad is subjected to thermal and mechanical stresses during the bonding process. Such stresses may damage or destroy sensitive layers and circuitry located under the bond pad. In addition, prior art methods of fabricating MOS transistors under bond pads have not addressed the latchup reliability issue. This issue is present when large active devices are placed under bond pads and in close proximity to circuitry of neighboring bond pads and/or neighboring circuitry outside the bond pad. Furthermore, the area underneath bond pads is very limited due to the need to minimize bond pad area.
None of the prior art bond pad structures has been entirely satisfactory with respect to die area and reliability. Accordingly, there is a need for new and improved bond pad structures and methods of making bond pad structures.